1. Field of the Invention
The present invention relates to a method for fabricating and assembling integrated circuit or memory chips on a circuit substrate or printed wiring board and, more particularly, for stacking such chips into a contacting layered stack, such that their planes lie parallel to and in contact-with the plane of the circuit substrate or printed wiring board, and to the parallelly stacked chip assembly manufactured by the method.
2. Description of Related Art and Other Considerations
Conventionally, integrated circuit and memory chips are mounted singly in a hermetic package, and the package leads are interconnected to a substrate or a printed circuit board. Alternately, the chips are mounted onto a circuit board in a hermetic hybrid package whose external leads are interconnected to the printed wiring board.
When space and volume are at a premium, use of such conventional mounting arrangements results in a less than optimal overall circuit density and a lower circuit speed. Specifically, presently used mounting arrangements consume relatively large amounts of space and volume, and thus lessen circuit density. Further, the relatively large spacing between the chips lowers circuit speed and increases capacitances, thereby causing slower signal propagation through the circuit.
These problems have been recognized in the packaging technology, as exemplified by U.S. Pat. No. 4,525,921 and 4,764,846. There, chips are stacked at right angles to the substrate and interconnected with edge metalizing circuitry. On one edge or face of the stack, the circuit lines terminate at metal bumps which are used to interconnect the stack directly to a substrate and its corresponding pattern of circuit pads. The chips are thus oriented so that their planes lie normal to the plane of the substrate.
The aim of these patents is to achieve a high density in the stack. However, as disclosed, for example, in U.S. Pat. No. 4,764,846, to enable the mounting of its individual chips and their carriers to a stack-carrying substrate, the leads from the chips must be extended to a single side, which consumes a relatively large area, thereby militating against the desired aim of high density.
It is also possible further to increase density by lapping material from the back side of the wafer prior to its being diced into thinned chips. This thinning is expensive, and adds to the cost of the stack.
The bump mounting method of the stack is also costly, and its use in producing reliable connections is uncertain for use in such environments as airborne systems.